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https://github.com/UniXNU/NativeAdreno.git
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bluseliu50
1105b0ec8c
A thread checks the ring every 500 ms as msm's hangcheck_handler does: no fence progress with work pending and no CP progress (a6xx_progress, at most three retries) is a hang. Recovery follows recover_worker: the hung job's VM takes the fault and, unless it is the kernel's, becomes unusable; the fence moves past it; the board's restart hook resets the GPU and runs hw_init and CP init on the same ring; every later job is replayed with its own fence. Clients read the global fault count plus their own VM's, so only the guilty client sees its device lost. The ring gains restart, unfenced submission, a6xx_idle, progress state and the GBIF bus halt; CP init can run unfenced.
63 lines
2.8 KiB
C++
63 lines
2.8 KiB
C++
/* SPDX-License-Identifier: MIT */
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#include "NativeAdrenoCpInit.h"
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#include "AdrenoPM4.h"
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#include <IOKit/IOLib.h>
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/* Pinned definitions: CP_SQE_INSTR_BASE is the 64-bit register at dword offset
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* 0x0830 for A6XX..A7XX (a6xx.xml). CP_THREAD_CONTROL is opcode 0x17 with
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* CONCURRENT_BIN_DISABLE at bit 27, and CP_ME_INIT is opcode 0x48 with seven
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* payload words (adreno_pm4.xml). The payload values are a7xx_cp_init in
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* a6xx_gpu.c: mask BIT(0)|BIT(1)|BIT(3)|BIT(6)|BIT(8), three hardware
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* contexts, 0x20000000 error detection, 0x00000002 operation mode, the
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* power-up register list address and BIT(31) to read it. */
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enum : uint32_t {
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CpSqeInstrBase = 0x0830,
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CpThreadControlOpcode = 0x17,
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CpMeInitOpcode = 0x48,
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CpConcurrentBinDisable = 1u << 27,
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CpMeInitWords = 8,
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CpInitWords = 10
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};
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IOReturn NativeAdrenoCpInit::poison()
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{
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poisoned_=true;return kIOReturnIOError;
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}
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uint32_t NativeAdrenoCpInit::meInitMask()
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{
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return (1u<<0)|(1u<<1)|(1u<<3)|(1u<<6)|(1u<<8);
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}
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IOReturn NativeAdrenoCpInit::run(const NativeAdrenoRingIo *io,NativeAdrenoRing *ring,
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const NativeAdrenoCpInitConfig *config,uint32_t *fence,bool fenced)
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{
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if(!fence)return kIOReturnBadArgument;*fence=0;
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if(done_ || poisoned_)return kIOReturnNotReady;
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if(!io || !io->write32 || !ring || ring->poisoned())return kIOReturnBadArgument;
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if(!config || !config->sqe_iova || (config->sqe_iova&4095) ||
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config->sqe_iova>=UINT64_C(1)<<48 || !config->pwrup_reglist_iova ||
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(config->pwrup_reglist_iova&3) || config->pwrup_reglist_iova>=UINT64_C(1)<<48)
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return kIOReturnBadArgument;
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if(config->sqe_base_programmed) {
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uint32_t lo=0,hi=0;
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if(!io->read32 || io->read32(io->cookie,CpSqeInstrBase,&lo) || io->read32(io->cookie,CpSqeInstrBase+1,&hi) ||
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(((uint64_t)hi<<32)|lo)!=config->sqe_iova)return poison();
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} else if(io->write32(io->cookie,CpSqeInstrBase,(uint32_t)config->sqe_iova) ||
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io->write32(io->cookie,CpSqeInstrBase+1,(uint32_t)(config->sqe_iova>>32)))
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return poison();
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uint32_t words[CpInitWords]={0};
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if(AdrenoPM4Type7(CpThreadControlOpcode,1,&words[0])!=AdrenoPM4Success ||
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AdrenoPM4Type7(CpMeInitOpcode,7,&words[2])!=AdrenoPM4Success)return poison();
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words[1]=CpConcurrentBinDisable;
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words[3]=meInitMask();
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words[4]=0x00000003; /* hardware contexts */
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words[5]=0x20000000; /* error detection */
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words[6]=0x00000002; /* operation mode */
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words[7]=(uint32_t)config->pwrup_reglist_iova;
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words[8]=(uint32_t)(config->pwrup_reglist_iova>>32);
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words[9]=1u<<31; /* read registers from the list */
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uint32_t value=0;
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const IOReturn status=fenced?ring->submit(words,CpInitWords,&value):ring->submitUnfenced(words,CpInitWords);
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if(status)return poison();
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done_=true;*fence=value;
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return kIOReturnSuccess;
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}
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